Through-silicon-vias are electrically conductive structures that extend from the back surface to the front surface of the silicon substrate of integrated circuits. A dielectric liner between the electrically conductive core and the silicon substrate prevents the electrically conductive core from shorting to the silicon substrate. During fabrication, it is necessary to stress test these vias during the fabrication process. After stress testing, the integrated circuit chips are discarded regardless of whether the chips pass the stress test or not because of reliability concerns. This is expensive and wasteful. Accordingly, there exists a need in the art to eliminate the deficiencies and limitations described hereinabove.